Failure-Pattern-Based Memory Test Data Analysis for Failure Classification and Yield Improvement

• Main Authors: Lin, Bing-Yang, 林斌彥
• Other Authors: Wu, Cheng-Wen
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/97040471847690775321

博士 === 國立清華大學 === 電機工程學系 === 104 === Memories have been considered as one of the major drivers of CMOS technology, due to their high density, high capacity, critical timing, sensitivity, etc. Memory diagnosis is therefore important for technology and product development. In memory diagnosis, memory test data need to be collected and analyzed. However, as memory density and capacity continue to grow, the amount of test data also keeps increasing, making it difficult to extract useful information for further diagnosis and analysis. In this thesis, we propose a test data compression technique, which compresses the fail bitmaps into different failure formats, resulting in more compact storage and faster access in the future. Experimental results show that for memories with different failure distributions, the failure bitmaps can be compressed to 21.03-57.26% of their original size without information loss. For memory diagnosis, memory failure pattern identification is traditionally considered as a key task to speed up the memory diagnosis and failure analysis process. A memory failure pattern is defined as a topological distribution of fail bits in the memory array. The critical memory failure patterns (those are found frequently, so are the yield killers), however, may change in different memory designs and process technologies. It is difficult to consider all critical failure patterns beforehand as they are not be defined in advance. To solve this problem, we propose a memory failure pattern identification system, which can identify critical memory failure patterns from a large amount of memory failure bitmaps automatically, even if they are not defined in advance. In our experiment for 132,488 4-Mb memory failure bitmaps, the proposed failure pattern identification system can automatically identify 6 critical yet undefined failure patterns in minutes, in addition to all known patterns. In comparison, the state-of-the-art commercial tools need manual inspection of the memory failure bitmaps to identify the same failure patterns. Another approach to improve the memory yield is redundancy repair, which uses redundancy to repair (replace) faulty parts of memories. To ensure high repair efficiency and final product yield, it is necessary to explore and develop memory redundancy architectures carefully. However, due to different memory failure distributions and design constraints of memory architectures, it is difficult to explore the efficiency of different redundancy architectures thoroughly. To solve this problem, we propose Raisin-C, which can be used to simulate the repair rates of different memory redundancy architectures with 2D and 3D redundancy constraints. In our experiments, the repair rates of 10 different 3D redundancy architectures with 3 different redundancy analysis algorithms in a given failure pattern distribution are simulated. The experimental result shows that the difference of the repair rates between the most efficient and least efficient memory redundancy architectures is up to 49.42%. In addition, to improve the stack yield of channel-based 3D DRAM, in this thesis, we introduce two redundancy schemes, i.e., Cubical Redundancy Architecture 1 and 2 (CRA1 and CRA2) [1], and propose two 3D redundancy schemes, i.e., Configurable Cubical Redundancy Architecture 1 and 2 (CoCRA1 and CoCRA2). The difference between CRAs and CoCRAs is that the spare memory of CoCRAs is configurable to allow efficient repair of row, column, and cluster failures, while that of CRAs only has one type of spare configuration. In (Co)CRA1, the global spares that can be shared across dies are associated with each DRAM die as conventional DRAMs. In (Co)CRA2, we use an SRAM on the logic die as global spares, which have higher flexibility than CoCRA1. The experimental result shows that CoCRA1 can achieve 28.09% higher stack yield than the traditional redundancy architecture, with only 50% of its spare space. There is only 0.05% and 0.2% area overhead on the logic die and DRAM die, respectively. On the other hand, CoCRA2 can further improve the stack yield to almost 100%, but with 2.3 times higher area overhead than CoCRA1.