Tunable One-Shot Pulse Generator for Testing of Small Clock Delay Fault
碩士 === 國立清華大學 === 電機工程學系 === 104 === As the chip design is more complex and larger size, the clock network is also more critical in any synchronous system. In 3-D IC, it is especially difficult to design and test. Even though a small fault at the clock network, it could lead catastrophic failure to...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32843428365360736367 |