| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 104 === As the chip design is more complex and larger size, the clock network is also more critical in any synchronous system. In 3-D IC, it is especially difficult to design and test. Even though a small fault at the clock network, it could lead catastrophic failure to damage the system. Therefore, it is important to detect in the manufacturing test or functional test to prevent this failure. In this work, we propose a test method with bin concept to detect the small clock delay fault at clock network, and also equip with the Tunable One-Shot Pulse Generator to generate the test clock and test pattern to feed the circuit under test. The Tunable One-Shot Pulse Generator is designed in TSMC 90nm CMOS process using only standard cells. By this test method, we can diagnosis the faulty flip-flop which is affected by clock delay fault through the outlier analysis. It is easy in the procedure to execute test as like flush test, and the method does not modify the clock network of the circuit under test. Consequently, the test process will not bring the loading to the clock network of the circuit under test, and we does not need to change the test pattern for the different circuit under test.
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