An Image Sensor with 10-bit Column-Parallel Single-Slope ADC

碩士 === 國立清華大學 === 電子工程研究所 === 104 === In this work, an image sensor with photovoltage-sensing pixels is designed and fabricated. A digital correlated double sampling circuit is designed to cancel fixed pattern noise. The implemented column-level ADC uses a single-slope architecture with 10-bit resol...

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Bibliographic Details
Main Authors:	Liu, Kuan Yen, 劉冠言
Other Authors:	Klaus Yung-Jane Hsu
Format:	Others
Language:	zh-TW
Published:	2016
Online Access:	http://ndltd.ncl.edu.tw/handle/52503616734742861802

id	ndltd-TW-104NTHU5428070
record_format	oai_dc
spelling	ndltd-TW-104NTHU54280702017-08-27T04:30:36Z http://ndltd.ncl.edu.tw/handle/52503616734742861802 An Image Sensor with 10-bit Column-Parallel Single-Slope ADC 具有行並列式十位元單斜率類比數位轉換器之影像感測器 Liu, Kuan Yen 劉冠言碩士國立清華大學電子工程研究所 104 In this work, an image sensor with photovoltage-sensing pixels is designed and fabricated. A digital correlated double sampling circuit is designed to cancel fixed pattern noise. The implemented column-level ADC uses a single-slope architecture with 10-bit resolution and 65 kHz sampling rate. All devices and circuits are integrated and implemented in a single chip. A 64x36 image array was fabricated with TSMC 0.18 μm CMOS technology. The array was designed for the specification of 30 frame/s in full HD. Measurement showed that the photodiode can respond to illuminance as low as 0.5 lux. At high light intensity, photodiode voltage change in log scale and the overall dynamic range is over 90 dB. The image array can respond to wide dynamic range of incident light. Klaus Yung-Jane Hsu 徐永珍 2016 學位論文 ; thesis 89 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立清華大學 === 電子工程研究所 === 104 === In this work, an image sensor with photovoltage-sensing pixels is designed and fabricated. A digital correlated double sampling circuit is designed to cancel fixed pattern noise. The implemented column-level ADC uses a single-slope architecture with 10-bit resolution and 65 kHz sampling rate. All devices and circuits are integrated and implemented in a single chip. A 64x36 image array was fabricated with TSMC 0.18 μm CMOS technology. The array was designed for the specification of 30 frame/s in full HD. Measurement showed that the photodiode can respond to illuminance as low as 0.5 lux. At high light intensity, photodiode voltage change in log scale and the overall dynamic range is over 90 dB. The image array can respond to wide dynamic range of incident light.
author2	Klaus Yung-Jane Hsu
author_facet	Klaus Yung-Jane Hsu Liu, Kuan Yen 劉冠言
author	Liu, Kuan Yen 劉冠言
spellingShingle	Liu, Kuan Yen 劉冠言 An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
author_sort	Liu, Kuan Yen
title	An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
title_short	An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
title_full	An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
title_fullStr	An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
title_full_unstemmed	An Image Sensor with 10-bit Column-Parallel Single-Slope ADC
title_sort	image sensor with 10-bit column-parallel single-slope adc
publishDate	2016
url	http://ndltd.ncl.edu.tw/handle/52503616734742861802
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An Image Sensor with 10-bit Column-Parallel Single-Slope ADC

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