| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 104 === The exponential progress in CMOS technology leads to the integrated circuits and systems operating with high speed, low power, a high integration level, and complicated functions. The concept of three-dimensional integrated circuit (3D IC) with through silicon vias (TSVs) technology has been proposed. By stacking chips three-dimensionally, the issue of long interconnects can be mitigated, and small form factors can be expected. However, the signal integrity problem is an important issue in 3D IC. Thus we propose using the Orthogonal Frequency-Division Multiplexing (OFDM) modulation to reduce the interferences from the channel. In addition, the OFDM scheme can be applied to different layers of the 3D IC, and the channels from these layers can be combined to a single channel for data transmission. As a result, not only the transmission speed can be increased, but the number of transmission channels can be reduced significantly.
The progress in IPD technology leads to small form factor and high performances of the system. Furthermore, the IPD technology can be combined with the three-dimensional integrated circuit (3D-IC) and through silicon vias (TSVs). Thus in this thesis, we establish the equivalent circuit model of inductive devices in the IPD, which will be employed in the design for the OFDM signal transmission in the 3D IC technology to further increase the data transmission rate and keeping the signal integrity.
In chapter 1, the overall structures of this thesis and the research motivations are introduced. Chapter 2 describes the principles of QPSK mapping and OFDM modulation. By using the QPSK mapping, the data rate can be two times faster than the BPSK signal. In addition, the Orthogonal Frequency-Division Multiplexing (OFDM) modulation can reduce the frequency selective attenuation and multipath delay spread, and release the inter symbol interference (ISI) problems. Also, the bandwidth efficiency of the system can be enhanced. Chapter 3 introduces the fundamental principles of the building blocks of receiver such as the low-noise amplifier (LNA), mixer, and analog-to-digital converter (ADC).
In chapter 4 and chapter 5, the transmitter and receiver for the overall OFDM modulation system are described, which are both fabricated in 90-nm CMOS process. First, the mathematics of the Inverse Discrete Fourier Transform (IDFT) and Discrete Fourier Transform (DFT) matrix in this OFDM modulation system are described based on matrices operation. Also, the building blocks of the transceiver, including DAC, balun, LNA, mixer, and ADC used in this thesis are discussed. The transmitter has an overall 0.980.72 mm2 chip area with power consumption of 4.15 mW, and the receiver has an overall 1.260.94 mm2 chip area and 21.6 mW power consumption. In addition, this thesis also presents the design of IPD inductive components, which can be used for the I/O transmitter and receiver design. The process design kit (PDK) is also developed as the scalable equivalent circuit model in chapter 6. The overall chip area is 7.56.2 mm2. Chapter 7 concludes this work and provides some research directions for the future study.
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