| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 104 === Time speculation has been widely used to achieve high performance in modern design as it uses the strategy of average-case timing optimization instead of worst-case timing optimization focusing on reducing worst-case path delay which rarely happens. Variable-latency design style is one research category of time speculation. As the variations in process and environment are hard to predict, the conventional variable-latency units (VLUs) designed at pre-silicon stage will experience significant performance loss. In this paper, we propose a novel sensor-based VLU (S-VLU) adapting to PVT variations and alleviating the floating mode problem of hold logic by using in-situ sensors to obtain real-time transition information in circuit. The S-VLU can achieve much higher accuracy. Moreover, we also propose a sensor placement strategy to achieve near-maximal performance gain. Experimental results on tsmc 40nm ISCAS designs show that the S-VLU achieves a 20.82% performance improvement as compared to a -6.67% improvement of traditional hold logic. The area overhead of the S-VLU is 18% compared to 15.2% of traditional hold logic. To the best of the authors’ knowledge, this is the first wok to address PVT variations in VLD.
|
|---|
