Architectural Evaluations on TSV Redundancy for Reliability Enhancement
碩士 === 國立清華大學 === 資訊工程學系 === 104 === Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can transmit through dies vertically. TSV may fail when a chip is...
Main Authors: | Chiu, Chien Pang, 邱建邦 |
---|---|
Other Authors: | Hwang, TingTing |
Format: | Others |
Language: | en_US |
Published: |
2016
|
Online Access: | http://ndltd.ncl.edu.tw/handle/24666372683301496822 |
Similar Items
-
Architecture of Redundant TSV for Clustered Faults
by: Chi, Kang, et al.
Published: (2015) -
Yield improvement of 3D ICs by TSV redundancy
by: Lin, Wei-Liang, et al.
Published: (2010) -
A review on TSV reliability
by: Wang Shuo, et al.
Published: (2021-02-01) -
Reliability-Enhancement Techniques for TSV-Based 3D RAMs
by: Li-Jung Chang, et al.
Published: (2013) -
A RF Redundant TSV Interconnection for High Resistance Si Interposer
by: Mengcheng Wang, et al.
Published: (2021-02-01)