Implementation of Core Element for Hyper-scalar Architecture

• Main Authors: Yu-Long Lai, 賴郁龍
• Other Authors: Jih-Ching Chiu
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/08486118480862917747

碩士 === 國立中山大學 === 電機工程學系研究所 === 104 === To meet the needs of a diverse range of programs and workloads, the design of multi-core processors is a major issue. Asymmetric multi-core processors (AMPs) design have been generated to the demand. The hyper-scalar microprocessor system architecture, which a kind of asymmetric multi-core processors with highly flexible applications. To achieve the increase of single thread performance in multi-core jointly execute, this architecture allows Virtual Shared Register Files (VSRF) to exchange data information within cores with the analysis of Instruction Analyzer (IA) when performs the same thread programs. In order to perform executing single-thread programs independently and accelerating single-thread programs within cores simultaneously, the hyper-scalar architecture propose core elements with out-of-order execution and in-order commit. This paper propose to implement a core element for hyper-scalar architecture. We puts in two data processing stage so that the core element support out-of-order execution and in-order commit with data processing unit. In addition, we benefit the programs with both considering the order of memory access and the adjustment of branch instruction. To applicable the hyper-scalar processor architecture, we discuss and implement the instruction operation mechanism, which can be section into three: First, Instruction Flow: To get up to the demands of out-of-order execution and in-order commit instructions, we add the data processing unit, instruction sequence table and register source table to the pipeline. Second, Memory Access Flow: Implementation of maintaining the correct order of memory access under the out-of-order execution by design of the memory unit. Third, Branch Ordered Flow: The computation of branch instructions should be saved until the instruction is completed in turn under the out-of-order execution. Finally we evaluate the result of simulation and testing through Verilog language and FPGA circuit synthesis. The result prove that the core element is applicable for the hyper-scalar claims of instruction flow control, memory access management and correct branch instruction execution. We can construct the two-core, four-core, or even multi-core hyper-scalar processors by the core element in the future.