An Efficient Pipelined Architecture for the Multi-precision Texture Unit

• Main Authors: Kuan-Hui Lee, 李冠輝
• Other Authors: Shiann-Rong Kuang
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/pftq5g

碩士 === 國立中山大學 === 資訊工程學系研究所 === 104 === As technology advances and the fully developed technology for 3-D graphics processing units, it has been widely applied in wearable devices. For wearable devices, the performance requirement of graphics processor unit performance is increasing, Unfortunately, these complex operations will consume a lot of power. Therefore, how to reduce the power consumption within the limited power of wearable devices has become an important issue. The texture unit is an indispensable part in the 3-D graphics processing units. The texture unit can make the image more details and high quality. In addition, it can use texture mapping to substitute complex computations, so that the overall performance and image quality of 3-D graphics processing units can be enhanced. Human eyes can’t clearly recognize a slight distortion of 3-D images. As a result, power savings can be achieved by selecting lower precisions mode when a little image distortion is acceptable. Besides, there is many complex computations in texture unit. These computations can be implemented by several dot product (DP4) instructions. Therefore, we design a dot product unit for texture unit to enhance the performance by a pipelined architecture. This thesis proposes a pipelined architecture for multi-precision texture unit. The architecture can change the computation precision to save power consumption. In addition, we add cache mechanism in texture unit to increase performance, and the dot product arithmetic unit is executed repeatedly to implement linear filter. As a result, the area of hardware circuit can be decreased. Finally, we perform pipelined scheduling for texture unit, and design the corresponding pipelined architecture that greatly enhances overall performance.