| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 104 === Fast rendering of computer graphics has gradually become an essential requirement for many embedded electronic devices. Ray-tracing can render more realistic graphics than the conventional depth-buffer based approach by mimicking the natural law of light transmission. How to achieve real-time ray-tracing in embedded environments has become a hot topic in recent years. In order to accelerate ray-tracing process, this thesis first proposes an efficient algorithm to test if a packet of rays and a node of the object tree intersect. By projecting the axis-alignment bounding box (AABB) of the testing node and the four corner rays of the packet into xy, xz, and zx planes, the intersection test can be carried out in two-dimensional coordinate world. The experimental result of the software simulation shows that up to 40% of execution time can be saved compared with the direct packet-ray rendering approach. Next, in order to further save the tree traversal time, this thesis proposes a hierarchal traversal scheme which adopts larger packets to traverse the object tree. Once it traverses down to the leaf nodes, the packets will be recursively divided into small sub-packets for further packet and node intersection tests. Our experimental results show that when rendering a small portion of large scenes, the proposed hierarchical traversal approach can achieve better speed-up. Based on the proposed algorithm, the thesis has developed a ray-tracing acceleration circuit which mainly comprises of one shadow ray generator, two traversal units, and eight intersection units. It has been synthesized by TSMC 90nm technology. The overall area of the proposed design is about 13,347,560〖μm〗^2, and can run up 170 Mhz.
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