| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 104 === With advances in semiconductor processing, the chip area becomes smaller and smaller, but not for power dissipation. In order to save energy and reduce the circuit power dissipation is important. The number of flip-flops in a system to use a lot, if you can reduce the power consumption of each flip-flop, the whole system power consumption will be significantly reduced.
In order to decrease power consumption, this thesis proposes two low-voltage flip-flops, which can be used for low voltage 0.6V operation. The clock frequency can achieve 250MHz, and can be applied to the 16-Bit Kogge-Stone adder .
UMC 0.18μm CMOS Logic & Mixed Mode 1P6M Process is used. The design specifications is at 0.6V, the data frequency is 10Mbps, and the clock frequency is 20MHz. Load capacitance is 10fF. In our proposed low-voltage flip-flop, C to Q propagation delay time is 2.86ns, the power consumption is 244nW, and power delay product (PDP) is 0.7fJ. Applied to 16-Bit Kogge-Stone adder, total layout area is 0.44 * 0.48 mm2.
|
|---|
