| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 104 === With the rapid advance in chip manufacturing technology, more and more functions and modules can be integrated into a single chip. Today, tens or hundreds of silicon intellectual property (IP) cores can be placed on a single chip. Such a system-on-chip (SoC) design, however, requires a high-performance, low-power on-chip interconnect to provide effective communication. Recently, the network-on-chip (NoC) architecture has been proposed for the interconnection framework of SoC. Furthermore, as Moore's Law will not be as effective in the future, 3D chip have been proposed and studied for the future chip manufacturing. Hence, the on-chip interconnect with 3D technology will be more critical for the SoC design.
This thesis presents the design of the NoC routing algorithms and architectures for future 3D VLSI chips. We focus on 3D mesh network routing with oversize IP cores in the NoC. In such a network, the network topology is no longer a conventional mesh. While some researchers have proposed their routing algorithms for 3D mesh NoC. Their designs focus on the regular 3D mesh with unit-size IP cores. Even though some researchers proposed the routing algorithms for 3D NoC with irregular topologies, they require costly routing tables with complex and slow routers.
We modify our previously proposed train routing algorithm and propose the effective 3D NoC routing algorithm with oversize IP cores, which is called XY-Elevator TRAIN (XY-EBT). We show that XY-EBT is deadlock-free and requires no routing tables. It provides the 3D chip with high-performance and low-cost chip communication. We have run many simulations for the performance evaluation of XY-EBT by the Booksim 2.0 simulator, and compare it with other routing designs. The results show that the XY-EBT achieves superior performance to other designs, especially when the router has two virtual channels at each input port.
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