| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 104 === As the VLSI advances into the nanometer era, modern chip design technology becomes more complex. As a result, the size of power/ground network dramatically increases; besides, the number of components connected on power/ground network is beyond millions, not to mention the number of resistances and capacitances in the power/ground network.
In the traditional design flow, in order to verify the accuracy of voltage and current in chip, the chip-package-board co-simulation is generally performed in late design stages. However, the co-simulation will cost a lot of time and computational resources. It’s necessary for us to develop a reduced core model of power/ground network to decrease the simulation time. The proposed model can not only shorten time-to-market but also strengthen the robustness of products.
We can develop the reduced core model by model-order-reduction (MOR) techniques. There are already many approaches such as graph-based methods TICER and projection-based methods PRIM and SIP. IR-drop is a major issue in such a large power/ground network causing power integrity problems. Due to the sparse characteristics of circuit, we implement the platform based on SIP in the thesis. The proposed node retention methods reserve dominant nodes in power/ground network and get reduced model as small as possible with acceptable accuracy. The experimental results shows that the proposed node retention methods can enhance accuracy up to 138 times compared to SIP with random node retention.
|
|---|
