| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 104 === In this thesis, a 2.5 GHz sub-harmonically injection locked phase locked loop (SILPLL) with fast self-calibrated timing technique is proposed. There are many issue in SILPLL, such as injection period, injection pulse width and injection timing. This study focus on the analysis of injection timing and proposed a new solution. Bad injection timing would cause many problems in the SILPLL, such as large jitter, large reference spur, and even unlocked. Adaptively tuning technique and self-calibration tuning technique was adapted to solve the injection timing problem. In SILPLL operation, the phase of injection timing would not change over time. Self-calibration tuning technique can turn off calibrated loop after finishing calibration. It would consume less power than the other. In calibration technique, it need to confront the longtime of calibration process. Because every time of tuning needs to wait the phase of phase locked loop (PLL) to stable, the calibration time was dragged. This study proposed a new self-calibrated technique with replica voltage control oscillator. It can separate self-calibrated loop from PLL and avoid disturbing PLL phase in the calibration process. This study realized a SILPLL with self-calibrated technique with low phase noise, low jitter and low reference spur.
This work is fabricated in 90 nm CMOS process with 9.71-mW power consumption. The measured phase noise at 1 MHz offset -105.7 dBc/Hz. The measured reference spur is -48.6 dBc. The measured rms jitter is 2.27 ps.
|
|---|
