| Summary: | 博士 === 國立中央大學 === 電機工程學系 === 104 === In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes USB 3.1 Gen1 specification as reference material.
In this thesis, the control loop of adaptive equalizer is embedded in phase detector of clock and data recovery to achieve low hardware complexity, meanwhile, using hybrid phase detector and current mode capacitance magnification method achieve small area and low power. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1V supply voltage. When CDR operates at 5 Gbps, the frequency of recovered clock is 2.5 GHz, peak-to-peak jitter of recovered clock is 15.56 ps, RMS jitter of recovered clock is 2.27 ps. When channel length is 0-m (short channel), peak-to-peak jitter of equalized data is 21.33 ps, RMS jitter of equalized data is 3.41 ps. When channel length is 1.5-m (long channel), peak-to-peak jitter of equalized data is 24 ps, RMS jitter of equalized data is 4.84 ps. The total power consumption of this work is 21.9 mW, the power consumption of CDR and adaptive equalizer are 15.1 mW and 6.8 mW. The chip area is 1.38 mm2 and the core area is 0.13 mm2.
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