| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 104 === The design and development of analog/mixed-signal(AMS) integrated circuits is becoming increasingly complex as technologies advances. Speeding up analog and mixed signal simulation is important in SoC design verification. Modeling analog circuit blocks by hardware description language and building their behavioral models is an efficient verification approach for AMS systems. To transform the circuits of designer into behavioral models automatically, in this thesis, we proposed an efficient structure analysis flow that can extract digital circuits in mixed-signal design automatically, and built a structure analysis platform to enable transforming Netlist files to Verilog automatically, replacing transistor-level design with behavior-level design and achieving the propose of speeding up simulation. With those behavioral models, the verification complexity and the simulation time can be reduced significantly. As shown in the experimental results on several circuits, the proposed approach is able to reach correct recognition with good accuracy.
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