A Design of Low Power Continuous Time Delta-Sigma Modulator for Biosignal Applications

碩士 === 國立中央大學 === 電機工程學系 === 104 === With the coming of aging societies and the emergence of civilized illness, modern people increasingly focus on their body monitoring, so that various wearable devices of blood pressure, blood glucose and heart rate sensors have been launched. However, it usually...

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Bibliographic Details
Main Authors: Ren-Chien Yang, 楊仁傑
Other Authors: Muh-Tian Shiue
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/73507449787105287930
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Summary:碩士 === 國立中央大學 === 電機工程學系 === 104 === With the coming of aging societies and the emergence of civilized illness, modern people increasingly focus on their body monitoring, so that various wearable devices of blood pressure, blood glucose and heart rate sensors have been launched. However, it usually be worn for long periods of time, so the lightweight and higher power efficiency are the key factors in considering. In general, biosignal detection system can be classified as sensor and the back-end processing circuit. The back-end processing circuit may be implemented by the integrated circuit (IC) to minimize the area. This thesis designs an analog to digital converter (ADC) for biosignal applications and implemented by continuous time delta-sigma modulator (CTDSM). The structure of the modulator is a third-order integrator and single bit quantizer. This ADC could process common biosignals and has enough resolutions to convert the analog signals to digital signals completely. In addition, the CTDSM also has the important property of implicit anti-aliasing filter (AAF), and it can relax the AAF front end and reduce power consumption in full system. Comparing to discrete time, the continuous time integrator can have lower power consumption to achieve the specification if both of them have the same type of integrator capacitor. In the end, the single bit quantizer can provide the best linearity and reduce the complexity of the circuit. The chip was implemented in 0.18 um CMOS technology and the core size is 0.8483 mm2. This work achieves 86 dB dynamic range and 12.6 bits ENOB in 10 kHz signal bandwidth with an oversampling ratio of 64. The power consumption is 140 uW under 1.8 V supply voltage.