| Summary: | 博士 === 國立中央大學 === 電機工程學系 === 104 === This study develops a K-band On-Off keying (OOK) transmitter and receiver for wireless sensor network (WSN) applications. A divide-by-3 and a divide-by-2 injection locked frequency divider are implemented by Darlington topology to achieve low power and wide locking range in tsmcTM CMOS 0.18 μm process. This study also develops K-band OOK transmitter and receiver that feature the performance of wideband, low power, low noise figure and high data rate in tsmcTM CMOS 90 μm technology.
In Chapter 2, the divide-by-two and divide-by-three injection-locked frequency dividers (ILFDs) using Darlington cell in tsmcTM 0.18 µm CMOS process. The Darlington cell has higher transconductance than traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-two ILFD to achieve lower power consumption and wide locking range. The measured locking range of the proposed divide-by-two ILFD is from 20.5 to 22.9 GHz. And the measured operation range of the divide-by-three ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are -138.3 and -140.35 dBc/Hz at an offset of 1-MHz when the input referred signals have phase noises of -132.54 and -131.5 dBc/Hz, respectively. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 × 0.75 mm2 and 0.77 × 0.79 mm2, respectively.
Chapter 3 presents a low-power and wideband CMOS low noise amplifier (LNA) with current-reused and gate-source transformer feedback techniques to obtain simultaneous noise and impedance matching from 14.7 to 26.7 GHz. The LNA also adopts an auxiliary amplifier to cancel the output third-order transconductance for linearity improvement. The LNA is fabricated in tsmcTM 90 nm CMOS technology and achieves a peak gain |S21| of 11.98 dB and a minimum noise figure (NF) of 2.8 dB. The measured input third-intercept point (IIP3) is -3.35 dBm at 17 GHz under dc power of 4.76 mW from a 0.8 V supply voltage. The overall figure-of-merit (FoM1) regarding gain, noise figure, bandwidth, OIP3, operation frequency, and dc power is up to 79.44 which is the highest one among the recently published works. The chip size of the fabricated LNA is 0.84 × 0.6 mm2.
Chapter 4 proposes a high energy-efficiency K-band OOK transmitter in tsmcTM 90 nm CMOS technology. The transmitter consists of a wideband voltage control oscillator (VCO), a frequency doubler and a switch-type power amplifier (PA) with a chip area of 0.6 × 0.92 mm2. The VCO adopts a parasitic capacitance reduction technique to enhance the tuning range to 20.5%. The designed transmitter achieves an output power of 3 dBm with a 500 Mbps data rate from 19 to 23.1 GHz at 22.3 mW power consumption. The correspondent energy-efficiency is 44 pJ/bit.
Chapter 5 proposes an OOK receiver which is realized in tsmcTM 90 nm CMOS process. The OOK receiver consists of a two-stage wideband LNA, a single-to-differential envelop detector with RC low pass filter and a 62.6 dB three-stage variable gain amplifier (VGA) with DC offset compensation circuit. The OOK receiver achieved a sensitivity of -47.6 dBm at 600 Mbps data rate under a pseudo random binary sequence (PRBS) 29-1 pattern. The receiver consumes a low power of a 9.5 mW which minimum average power is only 15.86 nW at the input power of -47.6 dBm. The chip area including the test pads is 1 × 0.81 mm2.
|
|---|
