Design Optimization of Single-/Dual-/Broad-Band FET Low-Noise Amplifiers and 5/60-GHz 0.18-um CMOS Dual-Mode Dual-Conversion Receiver

• Main Authors: Hsiao, Yu-Chih, 蕭語鋕
• Other Authors: Meng, Chinchun
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/7m7mq8

博士 === 國立交通大學 === 電信工程研究所 === 104 === This thesis describes the design optimization of single-band, dual-band and broadband inductively source-degenerated common-source FET LNAs using analytical formula of noise parameters derived through noise transformation matrix. The dual-band and broadband LC-ladder LNA designs can be directly expanded from the single-band LNA design using noise transformation matrix. The derived noise formulas of LNAs reveal that a simultaneous noise and input match can be obtained at a single frequency for a single-band LNA. For a concurrent dual-band LNA, the simultaneous noise match cannot be achieved at two different operating frequencies and thus a balanced design in noise performance is developed using noise transformation matrix. According to noise transformation matrix analytical method, the noise formulas of a broadband LC-ladder inductively source-degenerated common-source LNA and the related noise match network can be straightforwardly developed. Based on the established noise match network and well-known LC-ladder Chebyshev filter design method, the design optimization of the broadband LNA is also presented in this thesis. The presented optimal design algorithm of single-/dual-/broad-band LNAs can be applied to all of the FET devices such as MOSFET, MESFET and HEMT device. Finally, this thesis demonstrates a 5 GHz single-band, a 2.4/5 GHz concurrent dual-band and a 3~10 GHz broadband single-voltage-supply LNAs using 0.15 um pHEMT technology to verify design methodology. This thesis also presents a dual-mode dual-conversion receiver with two far-apart carrier frequencies, 5 GHz and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, in the standard 0.18 μm CMOS technology. The dual conversion architecture receives the 60 GHz mode using Schottky diodes at the first conversion stage and merges the 5 GHz mode at the second stage conversion. The GHz channel bandwidth selection of 60 GHz mode is achieved at the final IF2 stage while a narrow band active filter is inserted between the 5 GHz low-noise amplifier (LNA) and the second stage mixer to accomplish tens-MHz channel selection of 5 GHz mode in the 5 GHz RF path. The overlay of tens-MHz channel selection in the 5 GHz RF path with GHz channel selection in the final IF2 stage eliminates the severe gain-bandwidth trade-offs encountered if the tens-MHz channel selection is also done at the final IF2 stage.　　　　 In addition, a 2.4 GHz tunable active bandpass filter with two transmission zeros using the 0.18 um SiGe BiCMOS technology is also demonstrated in this thesis. The presented circuit topology employs a lumped ring structure and adds a perturbation capacitor to insert two transmission zeros for stopband rejection. To improve the passband insertion loss, a transformer-coupled Q-enhanced technique is employed to boost the Q-factor of the on-chip inductor. Moreover, three varactors are inserted in the filter design to achieve frequency tuning of the filter.