| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Theories, methodolgies, and applications of variabilities for CMOS devices have been elucidated, developed, and implemented. The variation of CMOS devices has been a significant issue as the devices are continuously scaled, in particular into the deep nano regime. The random dopant fluctuation(RDF) has become the most important issue that has received much more attentions more recently. However, there are other important factors that have seldomly been investigated. The variation-sources can be categorized into the process-induced and the stress-induced variations. The process-induced variations include the well-known RDF, the work function fluctuation(WFF) induced by un-uniform metal-grain-size, the line-edge-roughness(LER) induced by un-accurately exposed lithography, and the roughly deposited ultra-thin induced surface roughness variation(SRV); on the other hand, the stress induced variation considers the long-term-stress induced electric variations, including the random telegraph noise(RTN) induced by the interaction between the bulk traps and the channel carriers and by the random dopant fluctuation(RTF) induced by the disturbance of the interface traps. If one would like to design well-behaved and easily predictable devices, these various variation sources should be well-understood and under control.
Therefore, in this dissertation, the author has dedicated to the investigations of the variabilities of CMOS devices by using experimental methods so as to construct a simple, accurate, and the quantifiable theory and its methodology. In the chapter 2, the RDF has been thoroughly studied thourgh the profiling of the random-trap distribution along the channel direction by the discrete-dopant profiling technqiue. The discrete dopant profiling technique is based on the real measured data so as to directly sense the locations of the discrete dopants, which enables us to undertand the real distribution of the random dopants. In the chapter 3, the RTF has been examined for the devices after long-term stresses by the radom trap profiling technqiue. By using this technique, the profile of stress-induced traps can be mapped along the channel direction in ultra-scaled devices. This techniquie has earned a successful applictaion to the reliability study of the trigate CMOS devices, which makes it possible to design the next-generation trigate devcies with controlled variability and acceptable reliability. Furthmore, in the chapter 4, another big issue of variabilities after long-term stresses, that is, the random telegraph noise has been also carefully studied by using the 2D RTN profiling techniquie. With assistance of this techniquie, the 2D potential of RTN traps have been first employed. Morever, by using this techniquie, we can decouple the multi-level RTN signals into two interacting 2-level RTN traps and separatedly and individually study their characteristics. Finally, the impacts of multi-level RTN on the supressed window of the transfer curves for SRAM cells have induced as a new mechanism of the failure of transition in SRAM cells. In addition to the general variation issues of CMOS devices, such as RDF, RTF, and RTN, there is another important variation source in consideration of the unique 3D strucuture of trigate devices, that is, the surface roughness variation(SRV) because of the rough sidewall of the fins. In order to interpret the rough degree of the fin surfaces for a larger amount of devices statisitcally, an easy and usefull techniquie has been deduced and applied to extract the degree of surface roughness by using the concept of the gate-current variation for the first time in the word. The results have shown that the trigate devices with taller fin hieght have suffered much serious issues of surface roughness variation, which hurts the Vth variation and degrades the life-time of devices during stresses. Finally, all the viariation sources will reflect to the drian current of devices and its behaviours at the circuit level. In the end of this dissertation, the virtual source model has been involved to model the drain current in Id-Vgs and Id-Vds. Moreover, we have introduced the multi-variate analysis method to decompose the variations of drain current into few important factors, and by dealing with the variations of those individual affecting factors, the variation of drain currernt can be re-constructed in terms of a simple statistical expression so as to predict and to model the measured data. In this methodology, we construct the models of each drain current variation on each device and then the circuit level variation of basic logic gates, such as NAND, NOR, Inverter etc. via the commercially available Spice software. And finally, a simple, predictable, and accurate qusai-empirical fomula can be generalized to well predict the variation of very-large scale CMOS integrated ciruit.
These results and achievements obtained in this dissertation will help on the understanding of trigate devices as well as providing several important directions to the manufacturing of such devices. Innovations and applications have been accomplished in this systemtic study.
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