Built-in Phase Noise Measurement Technique for on Chip PLL
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Phase noise is the key performance indices of phase locked loops. In general, PLLs can be measured using spectrum analyzer or oscilloscope. The equipment and expenses takes too much cost. This thesis propose a phase noise measurement techniques. It can be i...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72myyf |
| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Phase noise is the key performance indices of phase locked loops. In general, PLLs can be measured using spectrum analyzer or oscilloscope. The equipment and expenses takes too much cost. This thesis propose a phase noise measurement techniques. It can be integrated to SoC, and measure many kinds of PLL system. The phase noise measurement techniques doesn’t use expensive instrument. In other words, testing cost can be reduced. This technique differs from the clock jitter measurement. It convert phase noise to digital signal directly. The composition of noise spectrum and noise power can be analyzed. The digital signal also support circuits to test or calibrate. The measurable maximum offset frequency is 1 MHz. The measurable in band noise floor is -114 dBc/Hz. This work fabricated in 65 nm CMOS technology. Supply voltage is 1.2 volt. The average power consumption of measurement techniques and timing generator is 3 mW. Its area is 0.03 mm2.
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