| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === A stable clock signal plays an important role in a system. As the speed of internal reference clock in the System-on-Chip (SOC) increased and the scaling down of the process, the effect of noise is more significant to the SOC. Therefore, a fast locking all-digital phase-locked loop (ADPLL) with higher-order filter is proposed in the thesis. At the frequency acquisition mode, the locking time is 5 cycles of the reference clock period by using the method of linear interpolation. On the other hand, at the phase tracking mode, the proposed ADPLL can select the loop filter as a first-order or a third-order with higher filtering capability. The ADPLL can attenuate the noise by using the higher-order filter.
The chip has been designed and implemented in TSMC 40nm GP 1P10M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the divided-by 2 circuit of duty-cycle correction circuit are from standard cell library, thus, it can be easily retargeted to others CMOS technology because of the cell-based nature. The total area of the ADPLL core is 0.0198mm2. The total locking time is 72 cycles of the reference clock. The total power consumption is 4.86mW at 5GHz output frequency and 96MHz reference clock. The power delay product is 0.972 mW/GHz.
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