Fabrication and Analysis of Amorphous In-Ga-Zn-O Thin-Film Transistors with Film-Profile-Engineering

• Main Authors: Shie, Bo-Shiuan, 謝博璿
• Other Authors: Lin, Horng-Chih
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/03258775007511195319

博士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In this dissertation, we have successfully fabricated and characterized high-performance amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with sub-micron channel length by using the novel “film-profile-engineering” (FPE) approach. In this approach in conjunction with proper deposition techniques, only one mask is needed for the TFT fabrication. Devices with Al2O3 or SiO2 gate insulator reveal decent performance, such as high field-effect mobility (17~20 cm2/V·s), steep subthreshold swing (SS) (60~80 mV/dec) and large ON/OFF current ratio (~109). The effects of various process parameters on the device’s electrical characteristics are also studied. Oxygen flow rate during the IGZO sputtering is found to affect SS and threshold voltage significantly, while the annealing conducted in a nitrogen environment can improve device’s stability. Interfacial interactions taking place at the interface between channel and S/D electrodes play an important role in the enhancement of device performance. Ar plasma treatment on the IGZO in the S/D regions can further improve the ON current due to the reduction in the S/D contact resistance. IGZO TFTs with organic passivation layer exhibit good electrical characteristics due to the lack of hydrogen-induced doping effect on the back side of channel as compared with the inorganic SiO2 and SiNX passivation layers deposited by plasma-enhanced chemical vapor deposition. We have further shrunk the channel length of the FPE devices down to sub-100 nm by incorporating photoresist trimming technique in the fabrication. The fabricated devices exhibit excellent characteristics as compared with the previously reported data. Our investigation also revealed that S/D series resistance is an inevitable issue to be solved for the ultra-short devices. To address the issues raised by the non-self-aligned FPE scheme, we proposed and demonstrated a simple method to obtain self-aligned bottom-gate FPE IGZO TFTs. It shows a significant reduction in OFF-state current thanks to a small gate-to-S/D overlap length (LOV), showing a great potential to boost circuit performance by reducing parasitic gate-to-S/D capacitances. Finally, we used TCAD simulation to investigate the thickness-dependent performance of inverted-staggered IGZO TFTs with channel thickness ranging from 10 to 50 nm. The analysis indicates that the reduced density-of-states as well as the higher carrier concentration (ND) in the thicker channel layer account for the better performance as observed from devices with a thicker channel. Furthermore, the performance improvement by the FPE configuration is also investigated via simulation, and the results indicate that FPE structure is beneficial for the oxide TFTs due to the smaller spreading resistance and lower DOS at the S/D regions as the ND > 5 × 1017 cm-3