A 1V SAR-DSM ADC for Audio Applications

• Main Authors: Hsu, Bo-Hsu, 許博豪
• Other Authors: Wu, Jieh-Tsorng
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/50329389656745601355

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === DSM ADCs is widely used in audio signal processing. It can perform noise shaping on spectrum, and the priciple is from loop filter (LF) and over-sampling to achieve high resolution. The transfer function of the integrators in LF dominates performance, that is a issue about designing high specification operational-amplifier (OP). Another issue is the dynamic range (DR) of DSM ADC, which decreases rapidly when input signal is larger than half sacle. SAR ADCs can achieve about 10~Bit resolution and 100~MHz sampling rate. Its power dissipation is quite low because of discarding the OP circuit. In modern low-power circuit, it is very common to use. And the complexity of circuit design is less than other ADCs if we want to implement. As to circuit design, the comparator dominates performance that it needs rigorously verifying. The specifications usually are limited by comparator and capacitors mismatching. This thesis described the design of a 1~V low voltage CMOS analog-to-digital converters (ADCs), which is to be used in audio application. The ADC combines with two different-type ADC, one is the successive approximation register (SAR) ADC, and the other is delta-sigma modulator (DSM) ADC. The hybrid ADC take advantages from this two ADCs above. The input siganl first is processed by SAR ADC to get coarse digital code. Then applying the code to DSM ADC to process residue, and we get the high resolution result finally. The residue is pretty low that the DR of DSM would increase. The proposed ADC architeture are a 6 bits SAR ADC and a second-order 1 bit DSM ADC. To process signal between this two ADC, we need two arrays of capacitors. The data weighted averaging (DWA) technique is used to reduce voltage error. Our target is to achieve 90~dB signal-to-noise ratio (SNR). The behavior design is verified by MATLAB and Verilog-A. We use TSMC 90nm COMS process in circuit simulation.