In-Situ Error Detection and Correction for Ultra-Low-Voltage VLSI Design

• Main Authors: Lin, Chi-Chun, 林琦竣
• Other Authors: Liu, Chih-Wei
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/91178510231830112498

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === With the increasing demand of biomedical electronic and wearable devices, low power is no longer the only consideration. Due to the small size of these product, the battery capacity is very limited, and therefore, how to use these energy efficiently is the most important considerations to design. Voltage scaling is an efficient technique to reduce power and energy consumption by scaling down the operating voltage. And when the operating voltage scaling down to near/sub-threshold voltage, there has a minimum energy consumption point. It means that if we want better energy efficiency, than we should let the circuit operate at near/sub-threshold voltage. However, design circuit for near-threshold voltage operation is challenging. The circuit operate under near-threshold voltage increase not only the circuit delay but also the delay variation. Unfortunately, conventional worst-case design in order to guarantee the chips are always correct in any corner, will sizing the circuit in large size and cause significantly area and power overhead. To solve this problem, the better-than-worst-case (BTWC) design technique was presented. Main idea of BTWC is design and optimize for common case and ignore worst-case in design time, so that the BTWC use the relaxed timing constrain to analyze and synthesize the design. When the worst-case happen in run time, the setup timing error will occur and need the setup timing error detection and correction. Therefore we need a efficiency and low area overhead error detection and correction. The proposed error detection and correction technique use the glitch detection to determine setup timing error by detect the signal is stable or not. When the error was detected, the correction will be trigger and gating clock immediately to give circuit one more cycle to finish computation. In order to verify purposed techniques, we implement a sensing platform and realize the proposed technique in the RISC processor at 40nm process. The proposed techniques has 0.36% area overhead of total area. And the proposed techniques has 46% energy saving or 116% throughput improve at same energy consumption compare with conventional worst-case design.