Impact of Spacer Design on Electrostatic Integrity and Performance of Multi-Gate InGaAs-OI FinFETs

• Main Authors: Lo, Chang-Ting, 羅章庭
• Other Authors: Su, Pin
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/7nu6be

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === This thesis investigates the impacts of spacer design for multi-gate InGaAs-OI FinFETs with self-aligned contact using TCAD simulations. Our study indicates that vacuum spacer can mitigate the degradation of electrostatic integrity induced by higher-k gate dielectric because of the reduction of drain field penetration. High-k devices with vacuum spacer also shows better inverter delay due to smaller fringing capacitance and larger ON current. In addition, the impacts of vacuum spacer on the stability and performance of 6T-SRAM are also investigated. However, source/drain-underlap devices with vacuum spacer suffer from larger source resistance compared to the nitride-spacer counterparts. Our study indicates that the use of corner spacer can reduce the source resistance, maintain smaller fringing capacitance, and result in better inverter delay. In addition, the InGaAs-OI FinFET with corner-spacer design possesses similar electrostatic integrity to the all-vacuum spacer counterpart.