A Comparative Study on Multisource Clock Network Synthesis
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Hybrid clock architecture offers a compromise between tree and mesh. While most of the relative works focus on tree-driven-mesh configuration, we are interested in the performance and optimization of multisource CTS flow provided by IC Com-piler, which appl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25851920279402363453 |