| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Since the larger scale of IoT applications nowadays, the great number and high diversity of sensor data make the whole system difficult to collect and store these data. A memory system with high bandwidth and large storage is on necessary in IoT routers. Furthermore, the FIFO memory is at the first place of the IoT routers to access lots of sensor data that can have a great influence on the performance of the whole router. As the result, a dynamic data management unit is proposed as the FIFO memory to increase the performance. Besides, the low-power issue is also considered in our design to achieve the low-power budget in IoT routers.
Our design is implemented via Synopsys Design Compiler based on TSMC 90nm technology at 50MHz. And the power consumption is simulated by using the power model. The latency of our design in low, medium and high injection load is 57.9%, 60.2% and 44.1% less than the distributed FIFO. The area of our design is 3.2% larger and the average power is 22.3% less than the distributed FIFO.
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