A System-on-Chip Design of Multi-channel Online Recursive Independent Component Analysis for Brain Computer Interface

• Main Authors: Chang, Jui-Chung, 張睿程
• Other Authors: Fang, Wai-Chi
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/e83ej2

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Recently, brain computer interfaces (BCIs) are developed to control machines through EEG directly. In order to enhance the feasibility, reliability, and accuracy of BCIs, EEG signals used for BCI applications should be acquired from human without artifacts in real-time. This thesis aims to design an effective and low power system on chip (SoC) of multi-channel EEG signal processor for real-time brain-computer interface (BCI) system. The architecture of the SoC comprises an independent component analysis (ICA) processor with a brain wave identity processor based on canonical correlation analysis (CCA) algorithm. Biomedical signals acquired from front-end sensor modules will be processed in ORICA processor and brain wave identity processor in real-time. In this thesis, a chip was designed based on an online recursive ICA (ORICA) algorithm, which provided an online analysis for recursive least square approximation. This type of ICA features that the output delay can be reduced and the capacity to train data by using a single sample signal extracted from each channel. Compared with other algorithms, ORICA enables real-time data processing, implemented on a chip, and does not require a lot of temporary data storage. However, the singular value decomposition (SVD) processor is widely used to complete the matrix inverse calculation during the system operation in this work. Because the SVD processor spends the most massive amount of computation in the whole system, its computation time and performance will directly affect the result of the system on the premise of the real-time and high accuracy requirements. The System-On-Chip design proposed in this thesis was implemented by using TSMC 40 nm CMOS technology. The core area of the chip is 975*975 μm2. The performance evaluation is done through Agilent 93000 SoC tester. The result shows that the power consumption is 10.895mW with 100 MHz operation frequency and 0.9 V core power. The separated EEG signals are acquired in 0.0078125s after each EEG sample. This work includes a high accuracy ICA processing and a brain wave identification to provide a more accurate EEG information extraction to various BCI systems in real-time.