Scalable Hybrid Barrier in NoC-based Multiprocessor Systems
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104
Main Authors: | Tseng, Yu-Lun, 曾于倫 |
---|---|
Other Authors: | Lai, Bo-Cheng |
Format: | Others |
Language: | en_US |
Published: |
2015
|
Online Access: | http://ndltd.ncl.edu.tw/handle/pbkndh |
Similar Items
-
A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips
by: Malave-Bonet, Javier
Published: (2012) -
Energy-Aware Task Scheduling for NoC-based Dynamic Voltage Scalable System
by: Ssu-Wen Hung, et al.
Published: (2009) -
Run-time scalable NoC for virtualized FPGA based accelerators as cloud services
by: Kidane, Hiliwi Leake
Published: (2018) -
Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)
by: Wilson Mauricio Chicaiza, et al.
Published: (2013-11-01) -
The Design of a NoC-Based Sparse Matrix Multiplication System
by: Yi-sheng Lin, et al.
Published: (2012)