| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Epileptic seizure control is a popular issue in recent years due to 30% of the epileptic patients remain drug-resistant and only some patients are suitable for resection surgery. The multi-channel seizure detection is also an important issue. The multi-channel detection can have more chances to cover the seizure onset zone so that the seizure can be suppressed efficiently. To achieve the better seizure control efficiency, the accuracy and the latency are necessary to reach certain levels (Accuracy > 90%, Latency < 5 s).
In this thesis, a seizure detection algorithm with the training process and the simulation result is presented. The detection latency is 2.25s. For the data set, the sampling rate is 1024 Hz, 512 Hz or 256 Hz. However, in order to reduce the hardware complexity, the window length and the downsample issue are also simulated. The simulation result shows that with 1 s window and 128 Hz sampling rate, the accuracy can be up to 97.76%.
A DSP processor for the 16-channel seizure detection has been designed and implemented. There are two main feature extraction circuits: 128-point approximate entropy and 128-point fast Fourier transform. The entropy block occupies 0.17mm2 while the FFT block occupies 0.58mm2, and the area of the DSP processor is 1.74mm2 in TSMC 0.18-um process. The operating frequency of the processor is 6.758 MHz and the power is 5.5 mW.
To achieve better accuracy, the more complex algorithms are employed such as neural network (NN) and support vector machine (SVM). The simulation result shows that the multi-layer neural network can achieve the accuracy of 98.96% and the SVM is 99.25% so that the algorithms can provide a reliable detection results.
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