| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Heterogeneous many-core systems are widely adopted in execution system aiming at high performance computing and energy efficiency nowadays. A heterogeneous system consists of traditional scalar processors and throughput processors support a large quantity of parallel executions. Different type of processors are in charge of processing distinct data executions according to the benefit of their own architecture. During the executions, data will be transferred between the heterogeneous cores in order to elaborate the advantages of different cores to process the data more efficiently. According to the previous research, the data transfer and management in heterogeneous many-core system are the important factors influencing the overall performance. Furthermore, in contrast to scalar processor, the throughput processors intend to allocate the data to the adjacent place as doing high quantity parallel executions, and it is called data coalescing. For the data transfer and management issues of heterogeneous many-core system, this thesis proposes a scheme to do the asynchronous transfer to eliminate the waiting time of data transfer. Also, this thesis propose a hardware architecture to track the data access pattern and reallocate the data position for throughput processors. It could ameliorate the data coalescing and reduce the number of memory transactions and then improve the overall performance and memory usage efficiency. The proposed hardware tracking architecture will get more benefits when the parallelism is higher with the throughput processors. The experiments of this thesis show the proposed asynchronous transfer could hide the transfer latency and get 47% improvement and the proposed data tracking mechanism could reduce the 75% number of memory transactions.
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