Characterization of Gate-All-Around Nanowire Junctionless Poly-Silicon Thin Film Transistors Fabricated by Nitride Hard Mask Methods
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In this thesis, effectively scaled poly-Si nanowire (NW) junctionless (JL) devices were formed by nitride hard mask methods simply with I-Line lithography. In the fabrication, in-situ doped poly-Si deposited by LPCVD is adopted to serve as the heavily-doped...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60817252445956240666 |
| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In this thesis, effectively scaled poly-Si nanowire (NW) junctionless (JL) devices were formed by nitride hard mask methods simply with I-Line lithography. In the fabrication, in-situ doped poly-Si deposited by LPCVD is adopted to serve as the heavily-doped channel of JL devices. Devices with channel length shorter than 200 nm and NW width around 15 nm have been successfully fabricated. The steep SS lower than 100 mV/dec is achieved owing to the good gate controllability by the gate-all-around structure. The Pelgrom plots are made to analyze and discuss the threshold voltage fluctuation. We also observe clear 2-level RTN characteristics in our scaled devices. RTN time constants are extracted to be around a few milliseconds, and dId/Id
are analyzed to probe the switching properties between discrete levels at different bias conditions.
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