Design of a Low-voltage 100Ks/s Successive Approximation Analog-to-Digital converter

• Main Authors: Wu, Cheng-Han, 吳承翰
• Other Authors: Sheu, Meng-Lieh
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/46307515872360358269

碩士 === 國立暨南國際大學 === 電機工程學系 === 104 === A low-voltage 100Ks/s successive approximation ADC for the sensor in protable and wearable products is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.6 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multil-metal sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption. The low-voltage 100kS/s successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS process provided by Chip Implementation Center (CIC). From the post-simulation results at 0.6 V supply voltage, 1.2 MHz operating frequency, 100 kS/s sampling rate, and 1.376 kHz input frequency, an SNDR of 61.379 dB (ENOB of 9.904 bits) is achieved with 0.478 μW power consumption. The FOM is 4.16 fJ/conversion. the INL is -0.687(LSB) to +0.625(LSB), the DNL is -0.499(LSB) to +0.500(LSB)。