Study of Sub-10 nm TFETs and W-Band CMOS Low Noise and Power Amplifiers

• Main Authors: Nguyen Van Kien, 阮文堅
• Other Authors: Lin,Yo-Sheng
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/83276121483562532827

博士 === 國立暨南國際大學 === 電機工程學系 === 104 === This thesis is organized two parts. The first part studies the tunnel field-effect transistors (TFETs). The tunneling mechanism, operation principles, modeling, and design of the TFET are explored. The main studies are short-channel effect, on-current improvement and scalability of the TFET devices. A new asymmetric junctionless TFET (AJ-TFET) is proposed and studied physical parameters, operation principles, scaling into sub-10 nm regimes, and the effects of quantum confinement in detail. The AJ-TFETs were numerically demonstrated that has excellent short-channel effects and favorable on-off switching. By using the proposed AJ-TFET architecture, the TFET can be successfully scaled down with feasible parameters to follow the scaling of Si-based CMOS technologies. To further enhance on-current of the AJ-TFETs, the low bandgap materials (III-V Semiconductors such as InAs, InSb etc. ) can be applied to the AJ-TFET architecture. The AJ-TFETs using III-V Semiconductors has revealed that has better short-channel effect and on-current than those of the conventional PIN-TFETs using III-V Semiconductors. The second part studies design and implementation of the W-band low noise and power amplifiers. The first design and implementation is a 62-77 GHz broadband LNA in standard 90 nm CMOS technology. To minimize loss, all of interconnection lines and the microstrip line (MSL) inductors are implemented on MT9. Three of simple common-source stages and short-circuit stubs are adopted to reduce number of passive and active components for obtaining optimal NF. The MOSFET size and bias voltage are chosen for optimum power consumption and NF minimization. The graphic method using noise circle, available gain circle, and source stability circle on Smith Chart is exploited for optimizing performance of the LNA. The proposed LNA achieves a measured 3 dB bandwidth of 15 GHz, a measured peak gain of 14.9 dB at 70 GHz, a power consumption of 20.6 mW, a measured S11 less than -10 dB in the working band, and the lowest measured noise figure of 7.0 dB at 69 GHz. The second design and implementation is a W-band power amplifier in 90 nm CMOS. The stable positive feedback of common-source configuration is used to improve gain of the proposed PA and maintain good PAE property of CS with ensuring unconditional stable. The traditional divider and combiner are substituted by Y-shaped power divider and combiner in the proposed PA to reduce loss and size. The load pull technique is applied at the final stage to optimize Pout. The proposed PA achieves a measured PSAT of 10.1 dBm, OP1dB of 6 dBm, PAE of 7.4%, gain of 19 dB at 86 GHz, and power consumption of 131 mW. The results have demonstrated that the proposed PA architecture is promising for communication systems.