| Summary: | 博士 === 國立成功大學 === 電機工程學系 === 104 === Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent energy efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also difficult to quickly evaluate the feasibility of realizing a SAR ADC for a given specification in a specified process node. This dissertation presents a systematic device sizing procedure for SAR ADCs based on designer experiences. A sizing tool based on the proposed design procedure is also implemented. Experimental results show that the generated SAR ADCs are highly competitive to many recently published works. Moreover, by employing the appropriate search algorithms according to the circuit characteristic, the sizing time is relatively short. In addition to the simulation results, three silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.
Besides, a comprehensive investigation on several important error sources for the SAR ADCs is also presented in this dissertation. The error sources investigated here include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential non-linearities (INL/DNL) of SAR ADCs those are resulted from these error sources are analyzed and addressed. A diagnosis procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also recommended in this dissertation.
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