Improvement Study on Wafer Grinding Warpage

• Main Authors: LIANG,TSAI-YUAN, 梁財源
• Other Authors: FANG,TE-HUA
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/23572034748848227456

碩士 === 國立高雄應用科技大學 === 機械與精密工程研究所 === 104 === Wafer polishing process, (WLCSP) processes in a process site, designated as Wafer Level Chip Scale Packaging wafer polishing by the customer to specify the thickness of the wafer manufacturing process, in recent years, growing in thin products, so customers demand is also more thinned wafer thickness, so the resulting wafers is increasing wafer Alice take after grinding, the present study was to explore how to improve Gao Qiao take degrees wafer polishing, and can improve the warping for the degree of correlation factor to reduce wafer warpage, thereby stabilizing the process, maximize productivity, and reduce process risk. and understand the IC manufacturing process will be backside grinding of the wafer thin, with Leader to customer needs packaging process. For example, in the application of smart cards, ground to a wafer thickness less than 300µm wafers even thinner it. Therefore, it will cause back grinding will produce stress and warpage, wafer stress is too large. You must use a special way to eliminate stress wafers. Can effectively reduce wafer warpage 3.33mm.