Static Random Access Memory

• Main Authors: WUN,JHONG-YU, 文忠宇
• Other Authors: SHIAU,MING-CHUEN
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/00882805430175692210

碩士 === 修平科技大學 === 電機工程碩士班 === 104 === This paper presents a new Static Random Access Memory (SRAM) circuit design, which includes a memory array, a plurality of control circuits, a plurality of precharge circuits, a standby-start circuit, a plurality of word line voltage level conversion circuits and a plurality of high voltage level control circuits. The memory array is composed of plural column cells and plural row cells, each row cell having a control circuit and a word line voltage level conversion circuit, and each column cell having a precharge circuits and a high voltage level control circuit. In Five-Transistor SRAM(5T SRAM), each memory cell includes a first inverter, including a PMOS transistor P11 and a NMOS transistor N11, a second inverter, including a PMOS transistor P12 and a NMOS transistor N12, and an access transistor N13. In Seven-Transistor SRAM(7T SRAM), each memory cell includes a first inverter, including a PMOS transistor P11 and a NMOS transistor N11, a second inverter, including a PMOS transistor P12 and a NMOS transistor N12, an access transistor N13, and reading transistors N14 and N15. Each control circuit is connected to the source electrodes of NMOS transistor N11 and N12 of each memory cell of a corresponding row cell, so as to control the source voltages of NMOS transistor N11 and N12 according to different operation modes. In writing mode, there are three kinds of circuit configurations of the source electrode of NMOS transistor N11: higher than ground voltage, opened circuit and keeping ground voltage but configured with smaller channel width to length ratio of NMOS transistor N11 and N12. The above three circuit configurations can effectively avoid the conventional single-bit-line of a SRAM exists a problem of considerable difficulty in writing a logic 1. In the first phase of the reading mode, lower the source electrode of the 5T SRAM NMOS transistor N11 from an original ground voltage to less than the ground voltage, and lower the source electrode of the 7T SRAM NMOS transistor N12 from an original ground voltage to less than the ground voltage, to speedup reading logic 0. In the second phase of the reading mode, bring the source electrode back to the ground voltage in order to reduce unnecessary power consumption. In standby mode, raise the source electrode of the NMOS transistor N11 and N12 of whole memory cells higher than the ground voltage in order to effectively reduce the leakage current. In the holding mode, keep the source electrode of the NMOS transistor N11 and N12 in original ground voltage. Furthermore, with the standby-start circuit is designed to effectively promote SRAM quickly enter standby mode, and thus improve the effectiveness of SRAM of standby. Finally, during the reading operation, the word line voltage level conversion circuits and the high voltage level control circuits can increase the on-resistance of NMOS transistor N13 and reduce the on-resistance of the NMOS transistor N11, and thus reduce the semi-selected cell disturbance of 5T SRAM and improve reading speed of 7T SRAM.