A Low-voltage Low-dropout Regulator
碩士 === 輔仁大學 === 電機工程學系碩士班 === 104 === This paper proposes a low-voltage low-dropout (LDO) regulator to provide the output voltage of 0.5V with input range from 0.6 ~ 0.9V. The low-voltage reference is generated with the zero temperature coefficient circuit composed by MOS transistors in subthreshold...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10463201607317098873 |
| Summary: | 碩士 === 輔仁大學 === 電機工程學系碩士班 === 104 === This paper proposes a low-voltage low-dropout (LDO) regulator to provide the output voltage of 0.5V with input range from 0.6 ~ 0.9V. The low-voltage reference is generated with the zero temperature coefficient circuit composed by MOS transistors in subthreshold condition. The error amplifier is modulated for the bulk voltage of the transistor to realize low-voltage operation. The low-voltage regulator is achieved with varying the bulk potential of the transistor to obtain the optimal performance between light load and heavy load. The maximum output current is 50mA. Designed with a CMOS 0.18μm technology, this LDO regulator occupies the area of 633μm ×630μm including pads. This active area is 0.097mm2.
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