The High-speed PCB Layout Design on Multi-board Systems with A Case Study of VC709

• Main Authors: Chi-Feng Wang, 王麒逢
• Other Authors: Molin Chang
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/gwce45

碩士 === 健行科技大學 === 電機工程系碩士班 === 104 === The clock on PCB design is increased rapidly, thus design is more and more difficult. How to reduce the signal reflection, crosstalk, ringing on transmission line? These issues have been paid more and more attention. The operation speed on Data bus between CPU and memory is often the highest part of the system. This also causes the system design becoming one of the most difficult subjects. There is a big change in the design from the SDRAM generation to the DDR SDRAM generation. Data is got once in a cycle change to be got two times in a cycle.That is, the fetch number of DDR SDRAM DATA will be two times the traditional SDRAM in the same clock. The topology architecture on DDR2 and DDR3 have been changed from T-topology to Fly-by topology. Meanwhile, the changes on the architecture from DDR3 to DDR4 are designed by Bank Group and POD. Because of that, the effectiveness of DDR4 have been improved greatly. Also, it started a whole new generation on memory. The alternation of generations change hardware and architecture to achieve best performance and lower working voltage. However, these changes make the process of PCB design more complicated and challenging. Nevertheless, memory is single element after all, compatibility on design and layout between other elements should be considered. Therefore, aside from undergoing stimulation analysis on the layout of memory, other elements should be adjusted and stimulated analysis at the same time to reach a better signal integrity. A prevalent product design architecture is memory module. This can make the design more flexible. Yet this brought about the problems on the connection between main board and daughter board. In this paper, we will use Xilinx Virtex-7 development board VC709 as main board, and Micron memory module DDR3 SO-DIMM as daughter board. Also,the context discusses the issues of memory layout design , connection between FPGA and memory, and it’s signal integrity by DesignLink in Allegro Cadence 16.5 SI.