Image Scaling Processor VLSI Design for Real-Time Multimedia Applications

碩士 === 中原大學 === 電子工程研究所 === 104 === The traditional image scaling technologies in academia and industry are very mature technologies and used widely. With the development of television, mobile phones and other display screen, 4k2k has gradually become the mainstream specifications currently. At the...

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Bibliographic Details
Main Authors: Hang-Ju Chang, 張恆茹
Other Authors: Shih-Lun Chen
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/eres3t
Description
Summary:碩士 === 中原大學 === 電子工程研究所 === 104 === The traditional image scaling technologies in academia and industry are very mature technologies and used widely. With the development of television, mobile phones and other display screen, 4k2k has gradually become the mainstream specifications currently. At the same time, the traditional technologies are already inadequate to be used since the considerations of hardware cost and the visual effects. In this thesis, we apply the low cost and high efficient image scaling technologies to implement the high quality scaling image integrated circuit design. For the view of the industry to considerate the cost and quality, the image scaling technologies are still fixed the magnification mainly. We propose a new linear interpolation algorithm and the bi-cubic interpolation algorithm, and the technique has the properties of low complexity and the high-quality, and reduces the chip area. However, due to the realization of the above techniques and failed to meet the prospective advanced academic research, we do not only present a hybrid interpolation algorithms model but also include the image scaling fuzzy theorem in this thesis. That contains the comparison and description of the adjustable spatial filter and the adjustable bi-cubic interpolation algorithm. This thesis proposes two methods, method A is the fixed spatial filter and the bicubic interpolation algorithm, and method B is the adjustable spatial filter and the adjustable bi-cubic interpolation algorithm. Compared with previous studies, the method A proposed in this thesis, the peak snr (PSNR) increases about 1.12 dB on average. For the hardware implementation, the proposed hybrid image scaling model integrated circuit design is implemented with the 0.18-micron CMOS process technology. The operation frequencies of both methods achieve 150MHz, the gate counts are 3.32K, and the chip area is 39,843 μm2. Compared with the previous circuit designs, the circuit design proposed in this thesis reduces at least 74.2% chip area.