Co-Optimization of Memory BIST Grouping and Test Scheduling under Power Constraints
碩士 === 中原大學 === 電子工程研究所 === 104 === Built-in self-test (BIST) is a well-known design technique for the embedded memory verification and fixing problem. As the chip design becomes more complex, the test time also becomes longer, which directly affects the cost of the testing. In addition to the test...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76d799 |