Co-Optimization of Memory BIST Grouping and Test Scheduling under Power Constraints

• Main Authors: Chang-Han Yeh, 葉昌翰
• Other Authors: Shih-Hsu Huang
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/76d799

碩士 === 中原大學 === 電子工程研究所 === 104 === Built-in self-test (BIST) is a well-known design technique for the embedded memory verification and fixing problem. As the chip design becomes more complex, the test time also becomes longer, which directly affects the cost of the testing. In addition to the test time, the built-in self-test circuit area, built-in self-test controller and memory routing wire length should also be included in the cost considerations. In this thesis, we propose a mixed integer linear programming approach to optimize the total test time under power constraints by taking into account the number of built-in self-test controller as well as the distances between BIST controller and memories. Experimental results show that our proposed method can achieve the minimum total test time and improve test efficiency by reducing the costs.