| Summary: | 碩士 === 國立中正大學 === 通訊工程研究所 === 104 === The low-density parity check (LDPC) codes have near-Shannon limit performance. But the complexity of LDPC decoding is too high to real-time systems. In the parallelization for high-throughput applications, the number of independent memory access usually dominates the coding throughput. Moreover, a class of large-girth LDPC codes usually has difficulties to realize the parallelization in the decoder.
We propose a code construction to take the number of required parallel decoding unit and the large-girth constraint into considerations at once. First, the parity check matrix would be split into the block-wise structure to fit the parallelization in the decoder. Second, the conversion of the cycle-checking inequalities can transform the girth issue into a linear system. In this paper, we represent the parity-check matrix by simplified matrix to check the constrains in construction easily.
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