Improved Hardware Implementation of Precoder-Matrix Indication for Periodic Channel-State Reports in 3GPP-LTE Downlink MIMO System

碩士 === 國立中正大學 === 通訊工程研究所 === 104 === As the wireless communications prevails, multiple-input multiple-output with orthogonal frequency division multiplexing (MIMO-OFDM) techniques have attracted much attention in recent years. Among the various MIMO techniques, the limited feedback precoding is the...

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Bibliographic Details
Main Authors: WU,JIA-RUEI, 吳佳叡
Other Authors: LIU,TSUNG-HSIEN
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/12592959539652234772
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Summary:碩士 === 國立中正大學 === 通訊工程研究所 === 104 === As the wireless communications prevails, multiple-input multiple-output with orthogonal frequency division multiplexing (MIMO-OFDM) techniques have attracted much attention in recent years. Among the various MIMO techniques, the limited feedback precoding is the focus of this thesis. The LTE downlink codebook is considered in this thesis. The precoding matrix at the transmitter side is selected from a finite-sized codebook. Using selection criterion we can pick out the most suitable precoding matrix from the codebook to against channel fading. We use MMSE Trace Criterion in this thesis, because it computational complexity is lower. We use LDLH matrix decomposition, and backward substitution to avoid matrix inversion operations. We improve previous thesis Complex Matrix Multiplication-1 utilizing LTE downlink codebook features to reduce the computational complexity, and improve speed of LDLH decomposition architectures and backward substitution architectures When the frequency is 170MHz,we can pick out codeword within 0.8ms. In 3GPP LTE standard periodic channel-state reports are often as once every 2ms. In this thesis, the designed hardware architecture was synthesized and verified in the Xilinx ISE 12.2 environment and also synthesized by Design Compiler. The designed architecture requires is 156.88K gates and work with frequency 170 MHz under the TSMC 90 nm CMOS technology. The designed architecture computes such precoding matrices with throughput rate 24.28M matrices/second.