Design of CMOS Branch Line Coupler with Raised-Ground Plane and Meandered-Line Technique

• Main Authors: HUNG,DING-LUN, 洪鼎倫
• Other Authors: CHANG,SHENG-FUH
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/9yeem5

碩士 === 國立中正大學 === 電機工程研究所 === 104 === Abstract The design of compact CMOS branch-line couplers in millimeter-wave bands was presented in this thesis. The ultra-compact chip size was achieved by the combination of capacitive load and ground-plane raise techniques. To demonstrate the proposed design, two branch-line couplers in Q- and V-band were designed in 0.18-m 1P6M standard CMOS technology. The first chip has the simulated 2.2 dB insertion loss, 1.6 dB coupled loss and larger than 15.2 dB return loss in 34-42 GHz. The phase imbalance is ±2°and the amplitude imbalance is±0.7 dB in 34-42 GHz. The chip size is 0.07 mm2, equivalent to 0.0012 λ_"g" ^2, excluding the input and output GSGSG pad area. The second chip achieved a measured insertion loss of 1.8 dB, the coupler loss of 2.1 dB, the return loss of 21.3 dB in 55-65 GHz. The measured phase imbalance is ±2°and amplitude imbalance is ±0.3 dB in 55-65 GHz. The chip size without pad is 0.035 mm2, equivalent to 0.0014 λ_"g" ^2. The measurement results agree very well with the simulation. This demonstrates the proposed capacitive load and the ground-plane raise technique can effectively reduce the chip size while keeping high coupler performance. Index Terms—branch-line coupler, capacitive load, millimeter-wave, CMOS, multilayer circuits, size reduction.