Deterministic BIST Using Dual LFSR for Low-power Scan Testing

• Main Authors: Fang-Hsu Lin, 林芳旭
• Other Authors: Wang-Dauh Tseng
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/41443642798832395256

碩士 === 元智大學 === 資訊工程學系 === 103 === Power consumption and the volume of test data are popular topics in VLSI　Testing field. These are the key factors that will determine the quality of the final data testing results in VLSI testing. Built-in self-test (BIST) architecture is a technique which can self-test and verify the data inside the equipment without any other externality, resulting the reduced amount of test data. Based on dual linear feedback shift register (LFSR) architecture, the aim of this study is to achieve a better testing data compression ratio under the premise that the reduction of power dissipation is similar to existing dual LFSR strategy. At the beginning, the LFSR architecture which composed of select-LFSR and compensate-LFSR compresses the test pattern from reseeding produce. Then, execute the final test pattern by AND or OR operation based on the selection of select-LFSR to reduce the number of 0 and 1 switching for lower power consumption. There are six test patterns generated by ATALANTA 2.0 using ISCAS’89 circuits was used in this study. The compression ratio was up to 81.16%, and the bit-switching reduction was up to 19.37% by comparing with original one. These data indicate that the LFSR architecture which composed of select-LFSR and compensate-LFSR may be promising tools to improve the data compression ratio and bit-switching reduction.