Implementation of a Novel Interleaved Three-Level Converter with Current Doubler Rectifier

• Main Authors: Nian,Yu-Bin, 粘煜彬
• Other Authors: Lin,Bor-Ren
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/68b647

碩士 === 國立雲林科技大學 === 電機工程系 === 103 === An interleaved three-level converter with the new current doubler rectifier is proposed in this thesis. It can be applied to high DC input voltage applications such as MRT power system. The main power of the MRT train is high DC input voltage. The main advantages of the proposed converter are zero voltage switching (ZVS) turn-on of all switches, the output ripple current cancellation and less voltage stress of output diodes. Two three-level converters connected in parallel are used to decrease the input current ripple and reduce the current stress and voltages stress of power switches. A new current doubler rectifier is used at the secondary side to reduce the output current ripple. Compared to the conventional center-tapped rectifier, the proposed current doubler rectifier has double conversion gain and high turn ratio. Therefore, the current stress on the primary side can be reduced. Finally, the simulation and measured results are presented to confirm the effectiveness of the proposed converter based on a prototype with 750-800V input and 48V/30A output.