Development and Applications of a MIPS Softcore

• Main Authors: Jia-Yan LIN, 林佳諺
• Other Authors: Wing-Kwong Wong
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/49277073193228646294

碩士 === 國立雲林科技大學 === 電子工程系 === 103 === In this study, Electric, which is a CMOS VLSI design system, is used to implement eleven instructions of 32-bit MIPS R2000. A non-pipelined version and a pipelined version have been implemented. There are five stages of running an instruction in general: instruction fetch, instruction decoding, execution, memory read/write, and write back. In the pipelined version, data hazards and control hazards are resolved. Bubble sort is implemented to evaluate both versions. The performance of the non-pipelined version is compared to that of Nios II/e and the performance of the pipelined version is compared to that of Nios II/f