H.264/AVC Scalable Video Extension Encoding System

博士 === 國立雲林科技大學 === 工程科技研究所 === 103 === H.264/AVC scalable video extension (SVC) is a standard based on H.264/AVC coding technology for multiple demanded video with a single video encoder. Compared with H.264/AVC, SVC introduces scalable coding characteristics for spatial, temporal, and quality scal...

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Main Authors: Tse-Min Chen, 陳澤民
Other Authors: Ching-Lung Su
Format: Others
Language:en_US
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/7vs8a8
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spelling ndltd-TW-103YUNT00280102019-05-15T22:08:04Z http://ndltd.ncl.edu.tw/handle/7vs8a8 H.264/AVC Scalable Video Extension Encoding System 可調式視訊編碼系統 Tse-Min Chen 陳澤民 博士 國立雲林科技大學 工程科技研究所 103 H.264/AVC scalable video extension (SVC) is a standard based on H.264/AVC coding technology for multiple demanded video with a single video encoder. Compared with H.264/AVC, SVC introduces scalable coding characteristics for spatial, temporal, and quality scalabilities that are suitable for unstable bandwidth communication environment or different decoding devices. However, the complexity of SVC is much higher than that of H.264/AVC. For real-time encoding by software SVC encoders, complexity reducing is necessary. In the dissertation, the low complexity Intra prediction is proposed, including fast Intra 4x4 prediction and Intra 16x16 prediction. To fast decide modes, Intra 4x4 adopts mode relationship between left, upper, and base layer (BL) macroblocks (MB). And, Intra 16x16 modes are estimated by the best mode of Intra 4x4 to speed up the Intra mode decision process. Otherwise, the hardware design of SVC encoders is the other trend for the real-time encoding purpose. Bandwidth and on-chip memory requirements are always both important issues in hardware implementations. And, the motion estimation (ME) module is critical path for two issues. The dissertation is also proposed the Inter prediction algorithm for the hardware encoder design of SVC that meets memory bandwidth and on-chip memory requirements. Clustered motion estimation and coding sequence reordering at macroblock and frame level processing are proposed and binifit to solve bandwidth and memory issues. Finally, the simulation results show the proposed Intra prediction algorithm reduces 52.53% complexity and only dropped 0.002dB video quality for Full HD resolution, under all Intra-frame coding with 3-layer (FullHD-HD-D1) spatial scalability. In addition, the proposed Inter prediction algorithm is compared to the previous research of Inter prediction, the proposed algorithm has a 49.20% lower external memory bandwidth and reduces the on-chip memory requirement by 80.45% with video quality enhancements of up to 0.087, 0.090, 0.078, and 0.070 dB for 4-layer (FullHD-HD-D1-CIF) spatial scalability, respectively. Ching-Lung Su 蘇慶龍 2015 學位論文 ; thesis 115 en_US
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description 博士 === 國立雲林科技大學 === 工程科技研究所 === 103 === H.264/AVC scalable video extension (SVC) is a standard based on H.264/AVC coding technology for multiple demanded video with a single video encoder. Compared with H.264/AVC, SVC introduces scalable coding characteristics for spatial, temporal, and quality scalabilities that are suitable for unstable bandwidth communication environment or different decoding devices. However, the complexity of SVC is much higher than that of H.264/AVC. For real-time encoding by software SVC encoders, complexity reducing is necessary. In the dissertation, the low complexity Intra prediction is proposed, including fast Intra 4x4 prediction and Intra 16x16 prediction. To fast decide modes, Intra 4x4 adopts mode relationship between left, upper, and base layer (BL) macroblocks (MB). And, Intra 16x16 modes are estimated by the best mode of Intra 4x4 to speed up the Intra mode decision process. Otherwise, the hardware design of SVC encoders is the other trend for the real-time encoding purpose. Bandwidth and on-chip memory requirements are always both important issues in hardware implementations. And, the motion estimation (ME) module is critical path for two issues. The dissertation is also proposed the Inter prediction algorithm for the hardware encoder design of SVC that meets memory bandwidth and on-chip memory requirements. Clustered motion estimation and coding sequence reordering at macroblock and frame level processing are proposed and binifit to solve bandwidth and memory issues. Finally, the simulation results show the proposed Intra prediction algorithm reduces 52.53% complexity and only dropped 0.002dB video quality for Full HD resolution, under all Intra-frame coding with 3-layer (FullHD-HD-D1) spatial scalability. In addition, the proposed Inter prediction algorithm is compared to the previous research of Inter prediction, the proposed algorithm has a 49.20% lower external memory bandwidth and reduces the on-chip memory requirement by 80.45% with video quality enhancements of up to 0.087, 0.090, 0.078, and 0.070 dB for 4-layer (FullHD-HD-D1-CIF) spatial scalability, respectively.
author2 Ching-Lung Su
author_facet Ching-Lung Su
Tse-Min Chen
陳澤民
author Tse-Min Chen
陳澤民
spellingShingle Tse-Min Chen
陳澤民
H.264/AVC Scalable Video Extension Encoding System
author_sort Tse-Min Chen
title H.264/AVC Scalable Video Extension Encoding System
title_short H.264/AVC Scalable Video Extension Encoding System
title_full H.264/AVC Scalable Video Extension Encoding System
title_fullStr H.264/AVC Scalable Video Extension Encoding System
title_full_unstemmed H.264/AVC Scalable Video Extension Encoding System
title_sort h.264/avc scalable video extension encoding system
publishDate 2015
url http://ndltd.ncl.edu.tw/handle/7vs8a8
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